For a given design, a hardware Trojan can be added into a particular specification, toplevel models, RTL level descriptions, gate-level netlist, chip layout or chip mask. The Trojan behaviour varies from a denial of service attacks such as aging acceleration of transistors and bus deadlocks to subtler attacks, such as bypassing the authentication and gaining unrecognized privileged access on a system for unauthorized adversaries, or data leakage through side channels of the hardware components.